The present invention relates generally to integrated circuit packages, and more specifically, to stackable chip-on-chip integrated circuit packages.
Computing systems require an increasing amount of functionality. Generally, functionality is added by increasing the number of integrated circuits on a microprocessor chip. On occasion, however, it is not possible or desirable to integrate all the needed functionality onto one chip. An alternative method of obtaining an increased amount of functionality is achieved by including more than one chip in a single semiconductor package. For example, semiconductor manufacturers have placed two or more chips side-by-side or on top of each other in a single package. Since each chip is often made by distinct manufacturing processes and different materials, and is optimized for distinct performance characteristics, such a package provides a range of functionality not possible when using a single chip.
The performance of a package with stacked chips is often significantly greater when compared to a package having chips which are coupled together in a side-by-side configuration. Stacked-chip configurations operate faster since the chips are brought physically close to each other, thereby allowing input and output signals to travel between each chip in less time. Additionally, stacked-chip configurations typically occupy a relatively small footprint. That is, stacked chips require less surface area on a circuit board than two chips which are coupled together in a side-by-side configuration. These performance improvements make the stacked-chip configuration very desirable.
Unfortunately, however, stacked chips present a problem in the semiconductor package assembly process since most of the existing semiconductor manufacturing infrastructure is customized for single chip configurations. It is very difficult to use single-chip manufacturing infrastructure to assemble packaged, stacked-chip devices. One known technique attempting to use the existing infrastructure to assemble stacked-chip devices reduces the thickness of each chip (i.e., by chemical etching) so that multiple chips may fit into infrastructure designed for single chips. The problem with this method is that the thinning process is time consuming and may damage the chips.
Ideally, stacked chip devices may be manufactured using specially tailored infrastructure. However, it would be very costly to acquire new infrastructure for such a purpose. Since the characteristics of stacked-chip configurations are very beneficial, an effective and cost-efficient method for manufacturing stacked-chip devices would be desirable.
The present invention provides a semiconductor package containing stacked devices which can be manufactured in an effective and cost-efficient manner. The stacked molded package of the present invention includes a semiconductor package attached to an electronic device. The semiconductor package includes a semiconductor die which is connected to a set of wire leads and is encapsulated within a protective molding material. Additionally, solder bumps within the molding material are attached to input and output contact points on the semiconductor die. Portions of the solder bumps are exposed through the surface of the molding material so that contact can be made with the electrical contacts of an electronic device stacked on the semiconductor package. The number and pattern of the semiconductor package""s solder bumps can be tailored to match the configuration of electrical contacts on the electronic device. The electronic device may be, for example, another semiconductor die or an opto-electronic transceiver. Also, heat slugs and heat sinks may be included within the semiconductor package and attached to the stacked electronic device.
The present invention also includes a method for manufacturing the stacked molded package. The method involves forming the semiconductor package within a molding chamber which is injected with the protective molding material. The method further involves lowering the top surface of the molding chamber onto the solder bumps of the semiconductor package. The contact between the top surface of the molding chamber and the solder bumps flattens a portion of the solder bumps and prevents the flattened portion from being covered with molding material. This flattened portion becomes the portion of the solder bumps which are exposed through the molding material. Manufacturing the semiconductor package may be performed with the current manufacturing infrastructure which is used to make semiconductor packages according to specific form factors. Such form factors may include SOP, QFP, DIP, BGA, etc. The ability to use current infrastructure provides great cost savings because specially tailored infrastructure for manufacturing stacked molded packages does not need to be acquired. Also, since only a single chip is packaged within the semiconductor package, the thinning of chips and the accompanying problems may be avoided. A stacked package is formed when an electronic device is attached to the molded package.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illusive by way of example the principles of the invention.